Name: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2021)
Start: 2021-06-21T10:00:00+02:00
End: 2021-06-23T16:50:00+02:00
Location: No location set

International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2021)

from Monday, June 21, 2021 (10:00 AM) to Wednesday, June 23, 2021 (4:50 PM)

Monday, June 21, 2021
11:45 AM Conference Opening 🔴 - Paul Chow (University of Toronto) Marco Platzner (Paderborn University) Christian Plessl (Paderborn University)
Conference Opening 🔴
- Paul Chow (University of Toronto)
- Marco Platzner (Paderborn University)
- Christian Plessl (Paderborn University)
11:45 AM - 12:00 PM
12:00 PM Monday Session
Monday Session
12:00 PM - 1:30 PM
Contributions

12:00 PM A Sorting Library for FPGA Implementation in OpenCL Programming 🔴 - Ryohei Kobayashi

12:30 PM A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool 🔴 - Hiroaki Suzuki

1:00 PM Automation of Domain-specific FPGA-IP Generation and Test ⚪️ - Yuya Nakazato
1:30 PM Break
Break
1:30 PM - 4:00 PM
4:00 PM Keynote: Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation 🔴 - Kosuke Tatsumura
Keynote: Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation 🔴
- Kosuke Tatsumura
4:00 PM - 5:00 PM
Session Chair: Kentaro Sano Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this talk, starting from the principles of SB, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such applications is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we discuss the parallelism of SB in depth and show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip.
5:00 PM
5:00 PM - 6:00 PM
Contributions

5:00 PM Introduction - Kentaro Sano Tomohiro Ueno

5:05 PM Lightning Talks - Andrew Putnam (Microsoft, USA) Kosuke Tatsumura Martin Herbordt (Boston University, USA) Taisuke Boku (University of Tsukuba, Japan) Tobias Kenter (Paderborn University)

5:20 PM Panel Discussion - Andrew Putnam (Microsoft, USA) Kosuke Tatsumura Martin Herbordt (Boston University, USA) Taisuke Boku (University of Tsukuba, Japan) Tobias Kenter (Paderborn University)
Tuesday, June 22, 2021
10:00 AM Keynote: Portable high-performance Python on CPUs, GPUs, and FPGAs 🔴 - Torsten Hoefler (ETH Zurich, Switzerland)
Keynote: Portable high-performance Python on CPUs, GPUs, and FPGAs 🔴
- Torsten Hoefler (ETH Zurich, Switzerland)
10:00 AM - 11:00 AM
Session Chair: Christian Plessl Python has become the de-facto language for scientific computing. Programming in Python is highly productive, mainly due to its rich science-oriented software ecosystem built around the NumPy module. As a result, the demand for Python support in High Performance Computing (HPC) has skyrocketed. However, the Python language itself does not necessarily offer high performance. In this work, we present a workflow that retains Python’s high productivity while achieving portable performance across different architectures. The workflow’s key features are HPC-oriented language extensions and a set of automatic optimizations powered by a data-centric intermediate representation. We also define a set of around 50 benchmark kernels written in NumPy to evaluate and compare Python frameworks for their portability and performance. We show performance results and scaling across CPU, GPU, FPGA, with 2.47x and 3.75x speedups over previous-best solutions and the first-ever Xilinx and Intel FPGA results of annotated Python.
11:00 AM
11:00 AM - 12:30 PM
Contributions

11:00 AM Simplifying the access and usability of High-Performance Computing 🔴 - Lena Oden (Fernuniversität Hagen, Germany)

11:30 AM On the Inevitability of Integrated HPC Systems and How they will Change HPC System Operations 🔴 - Martin Schulz (Technical University of Munich, Germany)
12:30 PM Tuesday Session 1
Tuesday Session 1
12:30 PM - 2:00 PM
Contributions

12:30 PM Kyokko: a vendor independent high speed serial communication controller 🔴 - Akinobu Tomori Yasunori Osana

1:00 PM StreamBrain: Am HPC framework for Brain-like neural networks on CPUs, GPUs, and FPGAs 🔴 - Artur Podobas

1:30 PM Benchmarking the Nvidia GPU Lineage: From Early K80 to Modern A100 with Asynchronous Memory Transfers 🔴 - Martin Svedin
2:00 PM Break
Break
2:00 PM - 6:00 PM
6:00 PM Tuesday Session 2
Tuesday Session 2
6:00 PM - 7:00 PM
Contributions

6:00 PM Accelerating Matrix Processing for MIMO Systems 🔴 (Received best paper award) - Miriam Leeser

6:30 PM Software-like Compilation for Data Center FPGA Accelerators 🔴 - James Thomas
Wednesday, June 23, 2021
11:45 AM PhD Forum
PhD Forum
11:45 AM - 1:00 PM
Contributions

11:45 AM Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS 🔴 - Tim Hansmeier

11:50 AM ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip 🔴 - Lennart Clausing

11:55 AM FPGA Acceleration of Short Read Alignment 🔴 - Konstantina Koliogeorgi

12:00 PM Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks 🔴 - Marius Meyer

12:05 PM I feel the need for speed: Exploiting latest generation FPGAs in providing new capabilities for high frequency trading 🔴 - Mark Klaisoongnoen

12:10 PM CoopCL: A Framework for Cooperative Execution of Data-parallel Kernels on Multi-device Platforms ⚪️ - Konrad Morén

12:15 PM Poster Session ⚪️
1:00 PM
1:00 PM - 2:30 PM
Contributions

1:00 PM Towards Real-Time Object Detection and Tracking at the Edge 🔴 - Morteza Biglari-Abhari (University of Aukland, New Zealand )

1:30 PM Energy-Efficient EdgeAI: A Cross-Layer Perspective 🔴 - Mohamed Shafique (New York University Abu-Dhabi (NYUAD), UAE and Tandon School of Engineering, New York University (NYU), USA)

2:00 PM Reconfigurable Computing Platforms for Accelerating Image Processing Applications ⚪️ - Diana Göhringer
2:30 PM Conference Closing and Award Session 🔴 - Christian Plessl (Paderborn Center for Parallel Computing)
Conference Closing and Award Session 🔴
- Christian Plessl (Paderborn Center for Parallel Computing)
2:30 PM - 2:45 PM
2:45 PM HEART steering committee meeting
HEART steering committee meeting
2:45 PM - 4:30 PM
Closed meeting