Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools

Name: Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools
Start: 2019-05-20T08:00:00+02:00
End: 2019-05-20T18:00:00+02:00
Location: Paderborn University

May 20, 2019

Paderborn University

Europe/Berlin timezone

Overview
Timetable

Contact

pc2-support@uni-paderborn.de

More details for this event can be found at:

https://pc2.uni-paderborn.de/teaching/trainings/intel-fpga-training/

Starts May 20, 2019, 8:00 AM

Ends May 20, 2019, 6:00 PM

Europe/Berlin

Paderborn University

L3.204