Name: Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools
Start: 2019-05-20T08:00:00+02:00
End: 2019-05-20T18:00:00+02:00
Location: Paderborn University

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Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools

Monday, May 20, 2019 - 8:00 AM

Monday, May 20, 2019