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Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools

Name: Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools
Start: 2019-05-20T08:00:00+02:00
End: 2019-05-20T18:00:00+02:00
Location: Paderborn University

Monday May 20, 2019, 8:00 AM → 6:00 PM Europe/Berlin

L3.204 (Paderborn University)

L3.204

Paderborn University

Description

More details for this event can be found at:

https://pc2.uni-paderborn.de/teaching/trainings/intel-fpga-training/

Contact

pc2-support@uni-paderborn.de

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